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High Resolution 6 GHz Fractional-N Frequency Synthesizer ADF4157
FEATURES
RF bandwidth to 6 GHz 25-bit fixed modulus allows subhertz frequency resolution 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the following frequency synthesizers: ADF4110/ADF4111/ADF4112/ADF4113/ ADF4106/ADF4153/ADF4154/ADF4156 Cycle slip reduction for faster lock times
GENERAL DESCRIPTION
The ADF4157 is a 6 GHz fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing subhertz frequency resolution at 6 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a - based fractional interpolator to allow programmable fractional-N division. The INT and FRAC registers define an overall N divider, N = INT + (FRAC/225). The ADF4157 features cycle slip reduction circuitry, which leads to faster lock times without the need for modifications to the loop filter. Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.
APPLICATIONS
Satellite communications terminals, radar equipment Instrumentation equipment Personal mobile radio (PMR) Base stations for mobile radio Wireless handsets
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP RSET
ADF4157
REFIN x2 DOUBLER 4-BIT R COUNTER /2 DIVIDER VDD DGND LOCK DETECT MUXOUT OUTPUT MUX SDOUT VDD RDIV NDIV THIRD ORDER FRACTIONAL INTERPOLATOR FRACTION REG MODULUS 225 INTEGER REG N COUNTER CURRENT SETTING RFCP4 RFCP3 RFCP2 RFCP1 RFINA RFINB + PHASE FREQUENCY DETECTOR - REFERENCE
CHARGE PUMP CSR
CP
HIGH Z
CE CLK DATA LE
32-BIT DATA REGISTER
AGND
DGND
CPGND
Figure 1.
Rev. 0
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05874-001
ADF4157 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description........................................................................... 8 Reference Input Section............................................................... 8 RF Input Stage............................................................................... 8 RF INT Divider............................................................................. 8 25-Bit Fixed Modulus .................................................................. 8 INT, FRAC, and R Relationship ................................................. 8 RF R Counter ................................................................................ 8 Phase Frequency Detector (PFD) and Charge Pump.............. 9 MUXOUT and LOCK Detect..................................................... 9 Input Shift Registers......................................................................9 Program Modes .............................................................................9 Register Maps.................................................................................. 10 FRAC/INT Register (R0) Map.................................................. 11 LSB FRAC Register (R1) Map .................................................. 12 R Divider Register (R2) Map .................................................... 13 Function Register (R3) Map ..................................................... 15 Test Register (R4) Map .............................................................. 16 Applications Information .............................................................. 17 Initialization Sequence .............................................................. 17 RF Synthesizer: A Worked Example ........................................ 17 Reference Doubler and Reference Divider ............................. 17 Cycle Slip Reduction for Faster Lock Times........................... 17 Spur Mechanisms ....................................................................... 18 Low Frequency Applications .................................................... 18 Filter Design--ADIsimPLL....................................................... 18 Interfacing ................................................................................... 18 PCB Design Guidelines for the Chip Scale Package.............. 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
7/07--Revision 0: Initial Revision
Rev. 0 | Page 2 of 20
ADF4157 SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 . Table 1.
Parameter RF CHARACTERISTICS (3 V) RF Input Frequency (RFIN) REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 3 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD Low Power Sleep Mode NOISE CHARACTERISTICS Phase Noise Figure of Merit 4 ADF4157 Phase Noise Floor 5 Phase Noise Performance 6 5800 MHz Output 7
1 2
B Version 1 0.5/6.0
Unit GHz min/max
Test Conditions/Comments -10 dBm/0 dBm min/max. For lower frequencies, ensure slew rate (SR) > 400 V/s. For f < 10 MHz, ensure slew rate > 50 V/s. For 10 MHz < REFIN < 250 MHz. Biased at AVDD/2 2 . For 250 MHz < REFIN < 300 MHz. Biased at AVDD/22.
10/300 0.4/AVDD 0.7/AVDD 10 100 32
MHz min/max V p-p min/max V p-p min/max pF max A max MHz max
5 312.5 2.5 2.7/10 1 2 2 2 1.4 0.6 1 10 1.4 VDD - 0.4 0.4 2.7/3.3 AVDD AVDD/5.5 29 10 -207 -137 -133 -87
mA typ A typ % typ k min/max nA typ % typ % typ % typ V min V max A max pF max V min V min V max V min/V max V min/V max mA max A typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ
Programmable. With RSET = 5.1 k. With RSET = 5.1 k. Sink and source current. 0.5 V < VCP < VP - 0.5. 0.5 V < VCP < VP - 0.5. VCP = VP/2.
Open-drain 1 k pull-up to 1.8 V. CMOS output chosen. IOL = 500 A.
23 mA typical.
@ 10 MHz PFD frequency. @ 25 MHz PFD frequency. @ VCO output. @ 2 kHz offset, 25 MHz PFD frequency.
Operating temperature of B version is -40C to +85C. AC-coupling ensures AVDD/2 bias. 3 Guaranteed by design. Sample tested to ensure compliance. 4 This figure can be used to calculate phase noise for any application. Use the formula -207 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen at the VCO output. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 6 The phase noise is measured with the EVAL-ADF4157EB1Z and the Agilent E5052A phase noise system. 7 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 2 kHz; RFOUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.
Rev. 0 | Page 3 of 20
ADF4157
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 . Table 2.
Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width
t4
CLK
t5
t2
DATA DB23 (MSB) DB22
t3
DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t7
LE
t1
LE
t6
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Figure 2. Timing Diagram
Rev. 0 | Page 4 of 20
ADF4157 ABSOLUTE MAXIMUM RATINGS
TA = 25C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted. Table 3.
Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Rating -0.3 V to +4 V -0.3 V to +0.3 V -0.3 V to +5.8 V -0.3 V to +5.8 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +125C 150C 260C 40 sec
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Package Type TSSOP LFCSP (Paddle Soldered) JA 112 30.4 Unit C/W C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 5 of 20
ADF4157 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RSET CP CPGND AGND RFINB RFINA AVDD REFIN
1 2 3 4 5 6 7 8 16 15
VP DVDD MUXOUT LE DATA CLK CE DGND
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TOP VIEW (Not to Scale)
ADF4157
14 13 12 11 10 9
CPGND AGND AGND RFINB RFINA
1 2 3 4 5
20 19 18 17 16
PIN 1 INDICATOR
CP RSET VP DVDD DVDD
15 14 13 12 11
TOP VIEW (Not to Scale)
ADF4157
MUXOUT LE DATA CLK CE
AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP 1 LFCSP 19 Mnemonic RSET Description Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between ICP and RSET is
I CPMAX = 25 . 5 R SET
2 3 4 5 6 7
20 1 2, 3 4 5 6, 7
CP CPGND AGND RFINB RFINA AVDD
8
8
REFIN
9 10 11 12 13 14 15
9, 10 11 12 13 14 15 16, 17
DGND CE CLK DATA LE MUXOUT DVDD
16
18
VP
where: RSET = 5.1 k. ICPMAX = 5 mA. Charge Pump Output. When enabled, this provides ICP to the external loop filter which, in turn, drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. AVDD has a value of 3 V 10%. AVDD must have the same voltage as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k. This input can be driven from a TTL or CMOS crystal oscillator, or it can be accoupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the five latches, the latch being selected using the control bits. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V 10%. DVDD must have the same voltage as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
Rev. 0 | Page 6 of 20
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ADF4157 TYPICAL PERFORMANCE CHARACTERISTICS
PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 A, phase noise measurements taken on the Agilent E5052A phase noise system.
10 5 0 6.00 5.95 CSR ON 5.90 5.85 CSR OFF 5.80 5.75 5.70 5.65 -100
-10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 8 9
05874-016
P = 4/5
P = 8/9
FREQUENCY (GHz)
-5
POWER (dBm)
0
100
200
300
400
500
600
700
800
900
FREQUENCY (GHz)
TIME (s)
Figure 5. RF Input Sensitivity
0 -5 -10
Figure 8. Lock Time for 200 MHz Jump from 5705 MHz to 5905 MHz with CSR On and Off
5.95
VDD = 3V 5.90 5.85 5.80 5.75 5.70 CSR ON
05874-017 05874-020
POWER (dBm)
-15 -20 -25 -30 -35 -40
FREQUENCY (GHz)
CSR OFF
5.65 5.60 -100
0
100
200
300
400
500
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
TIME (s)
Figure 6. Reference Input Sensitivity
0 -20 -40 -60 RF = 5800.25MHz, PFD = 25MHz, N = 232, FRAC = 335544, FREQUENCY RESOLUTION = 0.74Hz, 20kHz LOOP BW, ICP = 313A, DSB INTEGRATED PHASE ERROR = 0.97 RMS, PHASE NOISE @ 2kHz = -87dBc/Hz.
Figure 9. Lock Time for 200 MHz Jump from 5905 MHz to 5705 MHz with CSR On and Off
6
4
PHASE NOISE (dBc/Hz)
2
ICP (mA)
-80 -100 -120
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0
-2
-140 -160 1k
-4
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10k
100k FREQUENCY (Hz)
1M
10M
-6
0
0.5
1.0
1.5
2.0
2.5 VCP (V)
3.0
3.5
4.0
4.5
5.0
Figure 7. Phase Noise and Spurs (Note that the 250 kHz spur is an integer boundary spur; see the Spur Mechanisms section for more information.)
Figure 10. Charge Pump Output Characteristics, Pump Up and Pump Down
Rev. 0 | Page 7 of 20
05874-019
ADF4157 CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL 100k SW2 BUFFER
05874-005
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = fPFD x (INT + (FRAC/225)) (1) where: RFOUT is the output frequency of the external voltage controlled oscillator (VCO). INT is the preset divide ratio of the binary 12-bit counter (23 to 4095). FRAC is the numerator of the fractional division (0 to 225 - 1). fPFD = REFIN x [(1 + D)/(R x (1+T))] where: REFIN is the reference input frequency. D is the REFIN doubler bit. R is the preset divide ratio of the binary 5-bit programmable reference counter (1 to 32). T is the REFIN divide-by-2 bit (0 or 1). (2)
NC REFIN NC SW1 SW3 NC
TO R COUNTER
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a 2-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler.
BIAS GENERATOR 1.6V AVDD 2k 2k
RF R COUNTER
The 5-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 32 are allowed.
RF N DIVIDER FROM RF INPUT STAGE N = INT + FRAC/MOD TO PFD N-COUNTER
RFINA
RFINB
THIRD-ORDER FRACTIONAL INTERPOLATOR
05874-006
AGND
INT REG
MOD REG
FRAC VALUE
05874-007
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed.
Figure 13. RF N Divider
25-BIT FIXED MODULUS
The ADF4157 has a 25-bit fixed modulus. This allows output frequencies to be spaced with a resolution of fRES = fPFD/225 where fPFD is the frequency of the phase frequency detector (PFD). For example, with a PFD frequency of 10 MHz, frequency steps of 0.298 Hz are possible.
Rev. 0 | Page 8 of 20
ADF4157
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the R counter and the N counter and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level.
HI D1 U1 +IN CLR1 Q1 UP
INPUT SHIFT REGISTERS
The ADF4157 digital section includes a 5-bit RF R counter, a 12-bit RF N counter, and a 25-bit FRAC counter. Data is clocked into the 32-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of five latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2, and C1) in the shift register. These are the three LSBs, DB2, DB1, and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 6. Figure 16 shows a summary of how the latches are programmed.
PROGRAM MODES
Table 6 and Figure 16 through Figure 21 show how to set up the program modes in the ADF4157.
CP
DELAY
U3
CHARGE PUMP
HI
CLR2 DOWN D2 Q2
05874-008
U2 -IN
Figure 14. PFD Simplified Schematic
Several settings in the ADF4157 are double-buffered. These include the LSB FRAC value, R counter value, reference doubler, and current setting. This means that two events have to occur before the part uses a new value of any of the double-buffered settings. First, the new value is latched into the device by writing to the appropriate register. Second, a new write must be performed on Register R0. For example, updating the fractional value can involve a write to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should be written to first, followed by the write to R0. The frequency change begins after the write to R0. Double buffering ensures that the bits written to in R1 do not take effect until after the write to R0. Table 6. C3, C2, and C1 Truth Table
C3 0 0 0 0 1 Control Bits C2 0 0 1 1 0 C1 0 1 0 1 0 Register Register R0 Register R1 Register R2 Register R3 Register R4
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4157 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M4, M3, M2, and M1 (see Figure 17). Figure 15 shows the MUXOUT section in block diagram form.
THREE-STATE OUTPUT DVDD DGND R DIVIDER OUTPUT N DIVIDER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT SERIAL DATA OUTPUT CLK DIVIDER OUTPUT R DIVIDER/2 N DIVIDER/2 DGND
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DVDD
MUX
CONTROL
MUXOUT
Figure 15. MUXOUT Schematic
Rev. 0 | Page 9 of 20
ADF4157 REGISTER MAPS
FRAC/INT REGISTER (R0)
RESERVED
MUXOUT CONTROL
12-BIT INTEGER VALUE (INT)
12-BIT MSB FRACTIONAL VALUE (FRAC)
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
LSB FRAC REGISTER (R1)
RESERVED 13-BIT LSB FRACTIONAL VALUE (FRAC) (DBB) RESERVED CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
R DIVIDER REGISTER (R2)
REFERENCE DOUBLER DBB PRESCALER
DBB
RESERVED RESERVED
DBB 5-BIT R-COUNTER RESERVED CONTROL BITS
CURRENT SETTING
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(0)
RDIV2 DBB
RESERVED
CSR EN
FUNCTION REGISTER (R3)
CP THREE-STATE COUNTER RESET
U8 U7 0 0
PD POLARITY
SD RESET
RESERVED
RESERVED
CONTROL BITS
LDP
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U12 0 0 0 0 0 0 U11 U10 U9 C3(0) C2(1) C1(1)
TEST REGISTER (R4)
RESERVED CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(0)
05874-010
NOTES 1. DBB = DOUBLE BUFFERED BIT(S).
Figure 16. Register Summary
Rev. 0 | Page 10 of 20
PD
ADF4157
FRAC/INT REGISTER (R0) MAP
With R0[2, 1, 0] set to [0, 0, 0], the on-chip Frac/Int register is programmed as shown in Figure 17. used in Equation 1. See the INT, FRAC, and R Relationship section for more information.
Reserved Bit
The reserved bit should be set to 0 for normal operation.
12-Bit MSB FRAC Value
These twelve bits, along with Bits DB[27:15] in the LSB FRAC register (R1), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 1. These 12 bits are the most significant bits (MSB) of the 25-bit FRAC value, and Bits DB[27:15] in the LSB FRAC register (R1) are the least significant bits (LSB). See the RF Synthesizer: A Worked Example section for more information.
MUXOUT
The on-chip multiplexer is controlled by DB[30], DB[29], DB[28] and DB[27] on the ADF4157. See Figure 17 for the truth table.
12-Bit INT Value
These twelve bits control what is loaded as the INT value. This is used to determine the overall feedback division factor. It is
RESERVED
MUXOUT CONTROL 12-BIT INTEGER VALUE (INT)
12-BIT MSB FRACTIONAL VALUE (FRAC)
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
M4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
M3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
OUTPUT THREE-STATE OUTPUT DVDD DGND R DIVIDER OUTPUT N DIVIDER OUTPUT RESERVED DIGITAL LOCK DETECT SERIAL DATA OUTPUT RESERVED RESERVED CLK DIVIDER RESERVED RESERVED R DIVIDER/2 N DIVIDER/2 RESERVED
F12 0 0 0 0 . . . 1 1 1 1
F11 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
F2 0 0 1 1 . . . 0 0 1 1
F1 0 1 0 1 . . . 0 1 0 1
MSB FRACTIONAL VALUE (FRAC)* 0 1 2 3 . . . 4092 4093 4094 4095
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN REGISTER 0, AND THE 13-BIT LSB REGISTER STORED IN REGISTER 1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB x 213.
N12 0 0 0 0 . . . 1 1 1
N11 0 0 0 0 . . . 1 1 1
N10 0 0 0 0 . . . 1 1 1
N9 0 0 0 0 . . . 1 1 1
N8 0 0 0 0 . . . 1 1 1
N7 0 0 0 0 . . . 1 1 1
N6 0 0 0 0 . . . 1 1 1
N5 1 1 1 1 . . . 1 1 1
N4 0 1 1 1 . . . 1 1 1
N3 1 0 0 0 . . . 1 1 1
N2 1 0 0 1 . . . 0 1 1
N1 1 0 1 0 . . . 1 0 1
INTEGER VALUE (INT) 23 24 25 26 . . . 4093 4094 4095
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Figure 17. FRAC/INT Register (R0) Map
Rev. 0 | Page 11 of 20
ADF4157
LSB FRAC REGISTER (R1) MAP
With R1[2, 1, 0] set to [0, 0, 1], the on-chip LSB FRAC register is programmed as shown in Figure 18. value, and Bits DB[14:3] in the INT/FRAC register are the most significant bits. See the RF Synthesizer: A Worked Example section for more information.
13-Bit LSB FRAC Value
These thirteen bits, along with Bits DB[14:3] in the INT/FRAC register (R0), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 1. These 13 bits are the least significant bits of the 25-bit FRAC
RESERVED 13-BIT LSB FRACTIONAL VALUE (FRAC)
Reserved Bits
All reserved bits should be set to 0 for normal operation.
RESERVED
CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
F25 0 0 0 0 . . . 1 1 1 1
F24 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
F14 0 0 1 1 . . . 0 0 1 1
F13 0 1 0 1 . . . 0 1 0 1
LSB FRACTIONAL VALUE (FRAC)* 0 1 2 3 . . . 8188 8189 8190 8191
05874-012
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN REGISTER 0, AND THE 13-BIT LSB REGISTER STORED IN REGISTER 1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB x 213.
Figure 18. LSB FRAC Register (R1) Map
Rev. 0 | Page 12 of 20
ADF4157
R DIVIDER REGISTER (R2) MAP
With R1[2, 1, 0] set to [0, 1, 0], the on-chip R divider register is programmed as shown in Figure 19. With P = 4/5, NMIN = 23. With P = 8/9, NMIN = 75.
CSR Enable
Setting this bit to 1 enables cycle slip reduction. This is a method for improving lock times. Note that the signal at the PFD must have a 50% duty cycle in order for cycle slip reduction to work. In addition, the charge pump current setting must be set to a minimum. See the Cycle Slip Reduction for Faster Lock Times section for more information. Note also that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (DB6 in Register R3). It cannot be used if the phase detector polarity is set to negative.
RDIV2
Setting this bit to 1 inserts a divide-by-2 toggle flip flop between the R counter and the PFD. This can be used to provide a 50% duty cycle signal at the PFD for use with cycle slip reduction.
Reference Doubler
Setting DB[20] to 0 feeds the REFIN signal directly to the 5-bit RF R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 5-bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising edge and falling edge of REFIN become active edges at the PFD input. The maximum allowed REFIN frequency when the doubler is enabled is 30 MHz.
Charge Pump Current Setting
DB[27], DB[26], DB[25], and DB[24] set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with (see Figure 19).
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RFIN to the PFD input. Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operating the ADF4157 above 3 GHz, the prescaler must be set to 8/9. The prescaler limits the INT value.
5-Bit R Counter
The 5-bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 32 are allowed.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
Rev. 0 | Page 13 of 20
ADF4157
PRESCALER CURRENT SETTING REFERENCE DOUBLER RESERVED RESERVED RESERVED CSR EN RDIV2 5-BIT R-COUNTER RESERVED CONTROL BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(0)
C1 0 1
CYCLE SLIP REDUCTION DISABLED ENABLED
U1 0 1
REFERENCE DOUBLER DISABLED ENABLED
U2 0 1
R DIVIDER DISABLED ENABLED
P1 0 1
PRESCALER 4/5 8/9
ICP (mA) CPI4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CPI3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5.1k 0.31 0.63 0.94 1.25 1.57 1.88 2.19 2.5 2.81 3.13 3.44 3.75 4.06 4.38 4.69 5
R5 0 0 0 0 . . . 1 1 1 0
R4 0 0 0 0 . . . 1 1 1 0
R3 0 0 0 1 . . . 1 1 1 0
R2 0 1 1 0 . . . 0 1 1 0
R1 1 0 1 0 . . . 1 . 1 0
R COUNTER DIVIDE RATIO 1 2 3 4
29 30 31 32
Figure 19. R Divider Register (R2) Map
Rev. 0 | Page 14 of 20
05874-013
ADF4157
FUNCTION REGISTER (R3) MAP
With R2[2, 1, 0] set to [0, 1, 1], the on-chip function register is programmed as shown in Figure 20. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost. When a power-down is activated, the following events occur: 1. 2. 3. 4. 5. 6. All active dc current paths are removed. The synthesizer counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital lock detect circuitry is reset. The RFIN input is debiased. The input register remains active and capable of loading and latching data.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
- Reset
For most applications, DB14 should be set to 0. When DB14 is set to 0, the - modulator is reset on each write to Register 0. If it is not required that the - modulator be reset on each Register 0 write, this bit should be set to 1.
Lock Detect Precision (LDP)
When DB[7] is programmed to 0, 24 consecutive PFD cycles of 15 ns must occur before digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set.
RF Charge Pump Three-State
DB[4] puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation.
Phase Detector Polarity
DB[6] in the ADF4157 sets the phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0.
RF Counter Reset
DB[3] is the RF counter reset bit for the ADF4157. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0.
RF Power-Down
DB[5] on the ADF4157 provides the programmable powerdown mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation.
CP THREE-STATE COUNTER RESET
U8 U7
PD POLARITY
SD RESET
RESERVED
RESERVED
CONTROL BITS
LDP
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U12 0 0 0 0 0 0 U11 U10 U9 C3(0) C2(1) C1(1)
PD
U11 0 1 U12 0 1 SD RESET ENABLED DISABLED
LDP 24 PFD CYCLES 40 PFD CYCLES
U7 0 1
COUNTER RESET DISABLED ENABLED
U10 0 1
PD POLARITY NEGATIVE POSITIVE
U8 0 1
CP THREE-STATE DISABLED ENABLED
U9 0 1
POWER DOWN ENABLED
05874-014
DISABLED
Figure 20. Function Register (R3) Map
Rev. 0 | Page 15 of 20
ADF4157
TEST REGISTER (R4) MAP
With R3[2, 1, 0] set to [1, 0, 0], the on-chip test register (R4) is programmed as shown in Figure 21.
Reserved Bits
DB[31:3] should be set to 0 in this register.
CONTROL BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(0)
SET THESE BITS TO 0
Figure 21. Test Register (R4) Map
Rev. 0 | Page 16 of 20
05874-015
ADF4157 APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
After powering up the part, this programming sequence must be followed: 1. 2. 3. 4. 5. Test Register (R4) Function Register (R3) R Divider Register (R2) LSB FRAC Register (R1) FRAC/INT Register (R0) note that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the - circuit of the N divider.
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
In fast-locking applications, a wide loop filter bandwidth is required for fast frequency acquisition, resulting in increased integrated phase noise and reduced spur attenuation. Using cycle slip reduction, the loop bandwidth can be kept narrow to reduce integrated phase noise and attenuate spurs while still realizing fast lock times.
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be programmed: RFOUT = [N + (FRAC/225)] x [fPFD] where: RFOUT is the RF frequency output. N is the integer division factor. FRAC is the fractionality. fPFD = REFIN x [(1 + D)/(R x (1 + T))] where: REFIN is the reference frequency input. D is the RF REFIN doubler bit. R is the RF reference division factor. T is the reference divide-by-2 bit (0 or 1). For example, in a system where a 5.8002 GHz RF frequency output (RFOUT) is required and a 10 MHz reference frequency input (REFIN) is available, the frequency resolution is fRES = REFIN/225 fRES = 10 MHz/225 = 0.298 Hz From Equation 4, fPFD = [10 MHz x (1 + 0)/1] = 10 MHz 5.8002 GHz = 10 MHz x (N + FRAC/225) Calculating N and FRAC values, N = int(RFOUT/fPFD) = 580 FRAC = FMSB x 213 + FLSB FMSB = int(((RFOUT/fPFD) - N) x 212) = 81 FLSB = int(((((RFOUT/fPFD) - N) x 212) - FMSB) x 213) = 7537 where: FMSB is the 12-bit MSB FRAC value in Register R0. FLSB is the 13-bit LSB FRAC value in Register R1. int() makes an integer of the argument in brackets. (4) (3)
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when the loop bandwidth is narrow compared to the PFD frequency. The phase error at the PFD inputs accumulates too fast for the PLL to correct, and the charge pump temporarily pumps in the wrong direction, slowing down the lock time dramatically. The ADF4157 contains a cycle slip reduction circuit to extend the linear range of the PFD, allowing faster lock times without loop filter changes. When the ADF4157 detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. This outputs a constant current to the loop filter or removes a constant current from the loop filter (depending on whether the VCO tuning voltage needs to increase or decrease to acquire the new frequency). The effect is that the linear range of the PFD is increased. Stability is maintained because the current is constant and is not a pulsed current. If the phase error increases again to a point where another cycle slip is likely, the ADF4157 turns on another charge pump cell. This continues until the ADF4157 detects that the VCO frequency has gone past the desired frequency. It then begins to turn off the extra charge pump cells one by one until they are all turned off and the frequency is settled. Up to seven extra charge pump cells can be turned on. In most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. Setting Bit DB28 in the R Divider register (R2) to 1 enables cycle slip reduction. Note that a 45% to 55% duty cycle is needed on the signal at the PFD in order for CSR to operate correctly. The reference divide-by-2 flip-flop can help to provide a 50% duty cycle at the PFD. For example, if a 100 MHz reference frequency is available, and the user wants to run the PFD at 10 MHz, setting the R divide factor to 10 results in a 10 MHz PFD signal that is not 50% duty cycle. By setting the R divide factor to 5 and enabling the reference divide-by-2 bit, a 50% duty cycle 10 MHz signal can be achieved. Note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (DB6 in Register R3). It cannot be used if the phase detector polarity is set to negative.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually improves noise performance by 3 dB. It is important to
Rev. 0 | Page 17 of 20
ADF4157
SPUR MECHANISMS
The fractional interpolator in the ADF4157 is a third-order - modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM is clocked at the PFD reference rate (fPFD) that allows PLL output frequencies to be synthesized at a channel step resolution of fPFD/MOD. The various spur mechanisms possible with fractional-N synthesizers, and how they affect the ADF4157, are discussed in this section.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum; however, RF frequencies lower than this can be used providing the minimum slew rate specification of 400 V/s is met. An appropriate LVDS driver can be used to square up the RF signal before it is fed back to the ADF4157 RF input. The FIN1001 from Fairchild Semiconductor is one such LVDS driver.
FILTER DESIGN--ADIsimPLL
A filter design and analysis program is available to help the user implement PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLLTM software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed.
Fractional Spurs
In most fractional synthesizers, fractional spurs can appear at the set channel spacing of the synthesizer. In the ADF4157, these spurs do not appear. The high value of the fixed modulus in the ADF4157 makes the - modulator quantization error spectrum look like broadband noise, effectively spreading the fractional spurs into noise.
INTERFACING
The ADF4157 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When latch enable (LE) is high, the 29 bits that have been clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 6 for the latch truth table. The maximum allowable serial clock rate is 20 MHz.
Integer Boundary Spurs
Interactions between the RF VCO frequency and the PFD frequency can lead to spurs known as integer boundary spurs. When these frequencies are not integer related (which is the purpose of the fractional-N synthesizer), spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the PFD and the VCO frequency. These spurs are named integer boundary spurs because they are more noticeable on channels close to integer multiples of the PFD where the difference frequency can be inside the loop bandwidth. These spurs are attenuated by the loop filter. Figure 7 shows an integer boundary spur. The RF frequency is 5800.25 MHz, and the PFD frequency is 25 MHz. The integer boundary spur is 250 kHz from the carrier at an integer times the PFD frequency (232 x 25 MHz = 5800 MHz). The spur also appears on the upper sideband.
PCB DESIGN GUIDELINES FOR THE CHIP SCALE PACKAGE
The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. The user should connect the printed circuit board thermal pad to AGND.
Reference Spurs
Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechanism that bypasses the loop can cause a problem. One such mechanism is the feedthrough of low levels of on-chip reference switching noise out through the RFIN pin back to the VCO, resulting in reference spur levels as high as -90 dBc. Care should be taken in the PCB layout to ensure that the VCO is well separated from the input reference to avoid a possible feedthrough path on the board.
Rev. 0 | Page 18 of 20
ADF4157 OUTLINE DIMENSIONS
5.10 5.00 4.90
16 9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 22. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 3.75 BCS SQ 0.75 0.55 0.35 0.05 MAX 0.02 NOM COPLANARITY 0.08
11 10 6 5
0.60 MAX
16 15
PIN 1 INDICATOR
20 1
2.25 2.10 SQ 1.95 0.25 MIN 0.30 0.23 0.18
1.00 0.85 0.80 SEATING PLANE
12 MAX
0.80 MAX 0.65 TYP
0.50 BSC
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 23. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADF4157BRUZ 1 ADF4157BRUZ-RL1 ADF4157BRUZ-RL71 ADF4157BCPZ1 ADF4157BCPZ-RL1 ADF4157BCPZ-RL71 EVAL-ADF4157EB1Z1
1
Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Option RU-16 RU-16 RU-16 CP-20-1 CP-20-1 CP-20-1
Z = RoHS Compliant Part.
Rev. 0 | Page 19 of 20
ADF4157 NOTES
(c) 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05874-0-7/07(0)
Rev. 0 | Page 20 of 20

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